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integrated circuit systems, inc. icssstub32864a advance information 1166?10/05/05 recommended application: ddr2 memory modules provides complete ddr dimm solution with ics97u877 ideal for ddr2 400, 533, 667 and 800 product features: 25-bit 1:1 or 14-bit 1:2 configurable registered buffer supports sstl_18 jedec specification on data inputs and outputs supports lvcmos switching levels on c0, c1 and reset# inputs low voltage operation v dd = 1.7v to 1.9v available in 96 bga package drop-in replacement for icssstub32866 green packages available 25-bit configurable registered buffer for ddr2 truth table pin configuration 96 ball bga (top view) ball assignments a b 123456 c d e f g h j k l m n p r t a dcke nc v ref v dd qcke nc b d2 d15 gnd gnd q2 q15 c d3 d16 v dd v dd q3 q16 d dodt nc gnd gnd qodt nc e d5 d17 v dd v dd q5 q17 f d6 d18 gnd gnd q6 q18 g nc rst# v dd v dd c1 c0 h ck dcs# gnd gnd qcs# nc j ck# csr# v dd v dd zoh zol k d8 d1 9 gnd gnd q8 q1 9 l d 9 d20 v dd v dd q 9 q20 m d10 d21 gnd gnd q10 q21 n d11 d22 v dd v dd q11 q22 p d12 d23 gnd gnd q12 q23 r d13 d24 v dd v dd q13 q24 t d14 d25 v ref v dd q14 q25 123456 1:1 register (c0 = 0, c1 = 0) i nputs outputs rst# dcs# csr# ck ck# dn, dodt, dck e qn qcs# qodt, qcke h ll ll l l h ll hh l h h l l l or h l or h x q 0 q 0 q 0 h lh ll l l h lh hh l h h l h l or h l or h x q 0 q 0 q 0 h hl ll h l h hl hh h h h h l l or h l or h x q 0 q 0 q 0 h hh l q 0 h l h hh h q 0 h h h h h l or h l or h x q 0 q 0 q 0 l x or floating x or floating x or floating x or floating x or floating lll
icssstub32864a advance information 1166?10/05/05 2 ball assignments 1:2 register a (c0 = 0, c1 = 1) ball assignments 1:2 register b (c0 = 1, c1 = 1) a dcke nc v ref v dd qckea qckeb b d2 nc gnd gnd q2a q2b c d3 nc v dd v dd q3a q3b d dodt nc gnd gnd qodta qodtb e d5 nc v dd v dd q5a q5b f d6 nc gnd gnd q6a q6b g nc rst# v dd v dd c1 c0 h ck dcs# gnd gnd qcsa# qcsb# j ck# csr# v dd v dd zoh zol k d8 nc gnd gnd q8a q8b l d 9 nc v dd v dd q 9 aq 9 b m d10 nc gnd gnd q10a q10b n d11 nc v dd v dd q11a q11b p d12 nc gnd gnd q12a q12b r d13 nc v dd v dd q13a q13b t d14 nc v ref v dd q14a q14b 123456 a d1 nc v ref v dd q1a q1b b d2 nc gnd gnd q2a q2b c d3 nc v dd v dd q3a q3b d d4 nc gnd gnd q4a q4b e d5 nc v dd v dd q5a q5b f d6 nc gnd gnd q6a q6b g nc rst# v dd v dd c1 c0 h ck dcs# gnd gnd qcsa# qcsb# j ck# csr# v dd v dd zoh zol k d8 nc gnd gnd q8a q8b l d 9 nc v dd v dd q 9 aq 9 b m d10 nc gnd gnd q10a q10b n dodt nc v dd v dd qodta qodtb p d12 nc gnd gnd q12a q12b r d13 nc v dd v dd q13a q13b t dcke nc v ref v dd qckea qckeb 123456 general description this 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-v to 1.9-v vdd operation. all clock and data inputs are compatible with the jedec standard for sstl_18. the control inputs are lvcmos. all outputs are 1.8-v cmos drivers that have been optimized to drive the ddr-ii dimm load. icssstub32864a operates from a differential clock (ck and ck#). data are registered at the crossing of ck going high, and ck# going low. the c0 input controls the pinout configuration of the 1:2 pinout from a configuration (when low) to b configuration (when high). the c1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). the device supports low-power standby operation. when the reset input (rst#) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (vref) inputs are allowed. in addition, when rst# is low all registers are reset, and all outputs are forced low. the lvcmos rst# and cn inputs must always be held at a valid logic high or low level. to ensure defined outputs from the register before a stable clock has been supplied, rst# must be held in the low state during power up. in the ddr-ii rdimm application, rst# is specified to be completely asynchronous with respect to ck and ck#. therefore, no timing relationship can be guaranteed between the two. when entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. however, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. as long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of rst# until the input receivers are fully enabled, the design of the icssstub32864a must ensure that the outputs will remain low, thus ensuring no glitches on the output. the device monitors both dcs# and csr# inputs and will gate the qn outputs from changing states when both dcs# and csr# inputs are high. if either dcs# or csr# input is low, the qn outputs will function normally. the rst input has priority over the dcs# and csr# control and will force the outputs low. if the dcs#-control functionality is not desired, then the csr# input can be hardwired to ground, in which case, the setup-time requirement for dcs# would be the same as for the other d data inputs. package options include 96-ball lfbga (mo-205cc).
icssstub32864a advance information 1166?10/05/05 3 e m a n l a n i m r e tn o i t p i r c s e d l a c i r t c e l e s c i t s i r e t c a r a h c d n gd n u o r g t u p n i d n u o r g v d d e g a t l o v y l p p u s r e w o p l a n i m o n v 8 . 1 v f e r e g a t l o v e c n e r e f e r t u p n i l a n i m o n v 9 . 0 z h o e s u e r u t u f r o f d e v r e s e r t u p n i z l o e s u e r u t u f r o f d e v r e s e r t u p n i k ct u p n i k c o l c r e t s a m e v i t i s o p t u p n i l a i t n e r e f f i d # k ct u p n i k c o l c r e t s a m e v i t a g e n t u p n i l a i t n e r e f f i d 1 c , 0 cs t u p n i l o r t n o c n o i t a r u g i f n o c s t u p n i s o m c v l # t s r v s e l b a s i d d n a s r e t s i g e r s t e s e r - t u p n i t e s e r s u o n o r h c n y s a f e r d n a a t a d s r e v i e c e r t u p n i - l a i t n e r e f f i d k c o l c t u p n i s o m c v l # s c d , # r s c s t u p n i h t o b n e h w g n i h c t i w s s t u p t u o 4 2 d - 1 d s e l b a s i d - s t u p n i t c e l e s p i h c h g i h e r a t u p n i 8 1 _ l t s s 5 2 d - 1 d e h t d n a k c f o e g d e g n i s i r e h t f o g n i s s o r c e h t n o n i k c o l c - t u p n i a t a d # k c f o e g d e g n i l l a f t u p n i 8 1 _ l t s s t d o d d n a # s c d e h t y b d e d n e p s u s e b t o n l l i w t i b r e t s i g e r s i h t f o s t u p t u o e h t l o r t n o c # r s c t u p n i 8 1 _ l t s s e k c d d n a # s c d e h t y b d e d n e p s u s e b w o n l l i w t i b r e t s i g e r s i h t f o s t u p t u o e h t l o r t n o c # r s c t u p n i 8 1 _ l t s s 5 2 q - 1 q l o r t n o c # r s c d n a # s c d e h t y b d e d n e p s u s e r a t a h t s t u p u o a t a d s o m c v 8 . 1 # s c q l o r t n o c # r s c d n a # s c d e h t y b d e d n e p s u s e b t o n l l i w t a h t t u p t u o a t a d s o m c v 8 . 1 t d o q l o r t n o c # r s c d n a # s c d e h t y b d e d n e p s u s e b t o n l l i w t a h t t u p t u o a t a d s o m c v 8 . 1 e k c q l o r t n o c # r s c d n a # s c d e h t y b d e d n e p s u s e b t o n l l i w t a h t t u p t u o a t a d s o m c v 8 . 1 ball assignment
icssstub32864a advance information 1166?10/05/05 4 block diagram for 1:1 mode (positive logic) d c1 r qckea rst# ck ck# v ref dodt to 21 other channels 1d c1 r qcsa# dcs# 1d c1 r q1a d1 q1b * 0 1 d c1 r qodta dcke csr# *note: disabled in 1:1 configuration
icssstub32864a advance information 1166?10/05/05 5 block diagram for 1:2 mode (positive logic) 1d c1 r qckea rst# ck ck# v ref dodt to 10 other channels qckeb* 1d c1 r qcsa# dcs# qcsb#* 1d c1 r q1a d1 q1b * 0 1 1d c1 r qodta dcke qodt b* csr# *note: disabled in 1:1 configuration
icssstub32864a advance information 1166?10/05/05 6 absolute maximum ratings storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 2.5v input voltage 1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +2.5v output voltage 1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to vdd + 0.5v input clamp current . . . . . . . . . . . . . . . . . . . . 50 ma output clamp current . . . . . . . . . . . . . . . . . . . 50ma continuous output current . . . . . . . . . . . . . . . 50ma vdd or gnd current/pin . . . . . . . . . . . . . . . . 100ma package thermal impedance 3 . . . . . . . . . . . . . . . 36c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. notes: 1. the input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. this value is limited to 2.5v maximum. 3. the package thermal impedance is calculated in accordance with jesd 51. recommended operating conditions parameter min typ max units v dd 1.7 1.8 1.9 v ref 0.49 x v dd 0.5 x v dd 0.51 x v dd v tt v ref - 0.04 v ref v ref + 0.04 v i input voltage 0 v dd v ih ( dc ) dc input high voltage v ref + 0.125 v ih ( ac ) ac input high voltage v ref + 0.250 v il ( dc ) dc input low voltage v ref - 0.125 v il ( ac ) ac input low voltage v ref - 0.250 v ih input high voltage level 0.65 x v dd v il input low voltage level 0.35 x v dd v icr common mode input range 0.675 1.125 v id differential input voltage 0.600 i oh -8 i ol 8 t a 070c 1 guaranteed b y desi g n, not 100% tested in p roduction. description i/o supply voltage reference voltage operating free-air temperature reset#, c0, c1 clk, clk# low-level output current termination voltage high-level output current data inputs ma note: reset# and cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation. the differential in p uts must not be floatin g unless reset# is low. v
icssstub32864a advance information 1166?10/05/05 7 electrical characteristics - dc t a = 0 - 70c; v dd = 1.8 +/-0.1v (unless otherwise stated) symbol parameters v dd min typ max units v ik i i = -18ma -1.2 v oh i oh = -6ma 1.7v 1.2 v ol i ol = 6ma 1.7v 0.5 i i all inputs v i = v dd or gnd 1.9v -5 5 a standby (static) reset# = gnd 100 a operating (static) v i = v ih(ac) or v il(ac) , reset# = v dd 40 ma dynamic operating (clock only) reset# = v dd , v i = v ih(ac) or v il(ac) , clk and clk# switching 50% duty cycle. 39 /clock mhz dynamic operating (per each data input) 1:1 mode 19 dynamic operating (per each data input) 1:2 mode 35 data inputs 2.5 3.5 clk and clk# 2 3 reset# 2.5 notes: 1 - guaranteed by design, not 100% tested in production. c i v i = v dd or gnd i ddd reset# = v dd , v i = v ih(ac) or v il (ac) , clk and clk# switching 50% duty cycle. one data input switching at half clock frequency, 50% dut y c y cle i o = 0 i dd conditions v i = v ref 350mv v icr = 1.25v, v i ( pp ) = 360mv pf a/ clock mhz/data v 1.9v 1.8v
icssstub32864a advance information 1166?10/05/05 8 timing requirements (over recommended operating free-air temperature range, unless otherwise noted) symbol parameters min max units f clock clock frequency 410 mhz t w 1ns t act 10 ns t inact 15 ns setup time dcs before ck, ck , csr high; csr before ck, ck , dcs hi g h 0.6 ns dcs before ck, ck , csr low 0.5 ns dodt, dcke and data before ck, ck 0.5 ns dcs, dodt, dcke and data after ck, ck 0.4 ns par_in after ck, ck 0.4 ns 1 - guaranteed by design, not 100% tested in production. 2 - for data signal input slew rate of 1v/ns. 4 - clk/clk# signal input slew rate of 1v/ns. pulse duration, ck, ck high or low differential inputs active time (see notes 1 and 2) differential inputs inactive time (see notes 1 and 3) hold time t su t h notes: 3 - for data signal input slew rate of 0.5v/ns and < 1v/ns. setup time switching characteristics (over recommended operating free-air temperature range, unless otherwise noted) min typ max fmax 410 mhz t pdm 1 clk, clk# q 1.1 1.5 ns t pdmss 2 clk, clk# q 1.6 t phl reset# q 3 ns notes: 1. includes 350ps test-load transmission-line delay 2. guaranteed by design, not 100% tested in production. symbol v dd = 1.8v 0.1v units from ( in p ut ) to ( out p ut ) output buffer characteristics output ed g e rates over recommended operatin g free-air temperature ran g e (see fi g ure 7) min max dv/dt_r 1 4 v/ns dv/dt_f 1 4 v/ns dv/dt _ ? 1 1v/ns 1. difference between dv/dt_r (risin g ed g e rate) and dv/dt_f (fallin g ed g e rate) parameter v dd = 1.8v 0.1v unit
icssstub32864a advance information 1166?10/05/05 9 notes: 1. c l incluces probe and jig capacitance. 2. i dd tested with clock and data inputs held at v dd or gnd, and io = 0ma. 3. all input pulses are supplied by generators having the following chareacteristics: prr 10 mhz, zo=50 ? , input slew rate = 1 v/ns 20% (unless otherwise specified). 4. the outputs are measured one at a time with one transition per measurement. 5. v ref = v dd /2 6. v ih = v ref + 250 mv (ac voltage levels) for differential inputs. v ih = v dd for lvcmos input. 7. v il = v ref - 250 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos input. 8. v id = 600 mv 9. t plh and t phl are the same as t pdm . figure 6 ? parameter (v dd = 1. 8 v 0.1 v) r l = 1000 ? c l = 30 pf (see note 1) load circuit t w v icr v icr inpu t v ih v il voltage waveforms ? pulse duration v ref v ref inpu t t su t h v id v icr voltage waveforms ? setup and hold times v icr v id v icr output v ol v oh v tt v tt t phl t plh voltage waveforms ? propagation delay times t rphl v ol v oh v il v ih output voltage waveforms ? propagation delay times v dd /2 v tt t act t inact lv cmos input rst# voltage and current waveforms i dd (see note 2) 90% 10% inputs active and inactive times 0 v v dd tes t po i n t v dd /2 v dd /2 vcmos inp ut rst# tl=350ps, 50 ? dut ck# out tl=50 ? ck inputs v id ck ck ck ck r l = 100 ? ck tes t po i n t tes t po i n t r l = 1000 ? v dd measurement information
icssstub32864a advance information 1166?10/05/05 10 notes: 1. c l includes probe and jig capacitance. 2. all input pulses are supplied by generators having the following characteristics: prr 10mhz, z o = 50 ? , input slew rate = 1 v/ns 20% (unless otherwise specified). figure 7 ? output slew-rate (v dd = 1.8v 0.1v) c l = 10 pf (see note 1) load circuit ? high-to-low slew-rate measurement tes t po i n t dut out dt_f v ol v oh voltage waveforms ? high-to-low slew-rate measurement 80% output 20% dv_f r l = 50 ? c l = 10 pf (see note 1) load circuit ? low-to-high slew-rate measurement tes t po i n t dut out dt_r v ol v oh voltage waveforms ? low-to-high slew-rate measurement 80% output 20% dv _r r l = 50 ? v dd measurement information
icssstub32864a advance information 1166?10/05/05 11 ordering information icssstub32864az(lf)t - e - typ b ref b ref alpha designations for vertical grid (letters i, o, q & s not used) alpha designations for vertical grid (letters i, o, q & s not used) numeric designations for horizontal grid numeric designations for horizontal grid h typ h typ c ref c ref a b c d top view a1 3 2 1 4 seating plane seating plane c t 0.12 c d typ e d d1 d1 d1 d1 d1 - e - - e - - e - e1 typ typ d e t e horiz vert total d h b c min/max min/max min/max 13.50 bsc 5.50 bsc 1.30/1.50 0.80 bsc 6 16 96 0.40/0.50 0.25/0.41 0.75 0.75 11.50 bsc 5.00 bsc /1.2 0.65 bsc 6 16 96 0.38/0.48 0.27/0.37 0.875 0.875 mo-205 10-0055c all dimensions in millimeters ref. dimensions ----- ball grid ----- max. note: ball g rid total indicates maximum ball count for p acka g e. lesser q uantit y ma y be used. * source ref.: jedec publication 95, example: ics xxxx y z (lf) - t designation for tape and reel packaging lead free, rohs compliant (optional) package type h = lfbga (standard size: 5.5 x 13.50) hm = tfbga (reduced size: 5.0 x 11.50) revision designator (will not correlate with datasheet revision) device type prefix ics = standard device
icssstub32864a advance information 1166?10/05/05 12 revision history rev. issue date description page # 0.1 10/5/2005 initial release -

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